Two Phase CCD Clocking

	Interactive Java Tutorial
ATTENTION Our servers have detected that your web browser does not have the Java Virtual Machine installed or it is not functioning properly. Please install this software in order to view our interactive Java tutorials. You may download the necessary software by clicking on the "Get It Now" button below.

A two phase charge transfer CCD clocking scheme employs four gates for each pixel, with adjacent gates connected together as pairs. The two phase CCD scheme requires a more complex clocking arrangement than that described for the four phase and three phase CCD architectures. The shift register illustrated in this tutorial includes two pixel elements, for a total of eight gates aligned along a common axis to form a column. Each gate pair is connected to an alternate clock line and one of the gates in each pair is designed with an increased n-type doping level beneath the gate. When voltage is applied to the gate pair, the gate having the increased doping level has a more positive potential, which increases the depth of the charge storage area and results in a "step" in the potential energy profile.

The nature of electrostatic forces in the silicon substrate beneath the gates is determined by the voltage level applied to a particular gate by the clock input signal. High level voltages induce the formation of a potential "well" beneath the gate, whereas low level voltages form a potential barrier to electron movement. Clock lines are alternately pulsed, resulting in the charge packets (illustrated as blue "electrons" in the tutorial) being shifted along the CCD in a direction that is determined by the position of the extra doping. The requirement for only two clock phases reduces the complexity of the device, but at the expense of extra processing.