By incorporating on-chip multiplication gain, the electron multiplying CCD achieves, in an all solid-state sensor, the single-photon detection sensitivity typical of intensified or electron-bombarded CCDs at much lower cost and without compromising the quantum efficiency and resolution characteristics of the conventional CCD structure.
Interline charge-coupled device architecture is designed to compensate for many of the shortcomings of frame-transfer CCDs. These devices are composed of a hybrid structure incorporating a separate photodiode and a CCD storage region, protected with a mask structure, into each pixel element. Instructions for operation of the tutorial appear below the applet window.
Masked regions of the pixels are positioned alongside the photodiode elements in an alternating parallel array traversing the length of the CCD's vertical axis. Photodiodes in the array comprise the image plane and collect incoming photons projected onto the CCD surface by the camera or microscope lenses. After image data has been collected and converted into electrical potential by the image array, the data is then quickly shifted in a parallel transfer to the adjacent CCD storage area of each pixel element. The storage portion of the pixel element is illustrated as a cluster of gray-scale elements covered with an opaque mask adjacent to the red, green, and blue photodiode elements in each CCD. These pixel elements combine to form vertical columns that run from the serial shift register to the top of the array grid. An enlarged view of a single pixel element appears in the upper right hand corner of the applet.
Like the full-frame and frame-transfer architectures, interline CCDs undergo readout by shifting rows of image information in a parallel fashion, one row at a time, to the serial shift register. The serial register then sequentially shifts each row of image information to an output amplifier as a serial data stream. This action is controlled by the CCD Speed slider in the tutorial. Use the mouse cursor to shift the slider to the left to observe the CCD at slower shift speeds, or to the right for faster speeds. The entire process is repeated until all rows of image data are transferred to the output amplifier and off the chip to a analog-to-digital signal converter integrated circuit. Reconstruction of the image in a digital format yields the final photograph or photomicrograph.
During the period in which the parallel storage array is being read, the image array is busy integrating charge for the next image frame, similar to the operation of the frame-transfer CCD. A major advantage of this architecture is the ability of this device to operate without a shutter or synchronized strobe, allowing for an increase in device speed and faster frame rates. Image "smear", a common problem with frame-transfer CCDs is also reduced with interline CCD architecture. Drawbacks include a higher unit cost to produce chips with the more complex architecture, and a lower sensitivity due to a decrease in photosensitive area present at each pixel site. In addition, sampling errors are increased due to the reduced aperture size, and some interline CCD designs experience image "lag" as a result of charge transfer from photodiodes to the CCD storage areas.
Mortimer Abramowitz - Olympus America, Inc., Two Corporate Center Drive., Melville, New York, 11747.
Kevin John and Michael W. Davidson - National High Magnetic Field Laboratory, 1800 East Paul Dirac Dr., The Florida State University, Tallahassee, Florida, 32310.