Three Phase CCD Clocking

	Interactive Java Tutorial
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Charge transfer through CCD shift registers occurs after integration in order to relocate accumulated charge information to the sense amplifier, which is physically separated from the parallel pixel array. Several clocking schemes, including the three phase technique illustrated in this interactive tutorial, are utilized to transfer charge from the collection gates to the output node.

Three phase CCD clocking waveform complement improves spatial resolution over that obtained in four phase devices, yet requires only three gates per pixel. This scheme differs from four phase clocking by using only one storage gate and two barrier gates, which allows for faster frame rates and the fabrication of higher density and resolution CCDs. Another advantage of the technique is the formation of three independent polysilicon layers, one for each set of gate electrodes, so that clock phases are not forced to operate on two gates embedded in the same polysilicon layer. This innovation increases device fabrication yield.

A three phase CCD incorporates three individual polysilicon gate electrodes in each pixel cell, each of which requires a separate input clock signal to properly transport accumulated charge in a scheme that requires a more complex clocking arrangement than that of the four phase CCD. The shift register illustrated in the tutorial includes two complete pixel elements, for a total of six gates aligned along a common axis to form a column. The nature of electrostatic forces in the silicon substrate beneath the gates is determined by the voltage level applied to a particular gate by the clock input signal. High level voltages induce the formation of a potential "well" beneath the gate, whereas low level voltages form a potential barrier to electron movement.